DDECS-2007: April 11-13, Cracow, Poland The 10th IEEE Workshop on
Design and Diagnostics of Electronic
Circuits and Systems

April 11-13, 2007
Kraków, Poland
 Professor KRISHNENDU CHAKRABARTY www.ee.duke.edu/~krish/

"Design and Test of Microfluidic Biochips"


Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively, all in Computer Science and Engineering. He is now Professor of Electrical and Computer Engineering at Duke University. Dr. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Fellowship from the Alexander von Humboldt Foundation, Germany, and several best papers awards at IEEE conferences. His current research projects include: testing of system-on-chip integrated circuits; microfluidic biochips; microfluidics-based chip cooling; wireless sensor networks.

Prof. Chakrabarty is a Distinguished Visitor of the IEEE Computer Society for 2006-2007 and a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2006-2007. He is an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and System I, ACM Journal on Emerging Technologies in Computing Systems. He is an Editor of IEEE Design & Test of Computers and of the Journal of Electronic Testing: Theory and Applications (JETTA). Prof. Chakrabarty is a senior member of IEEE, a senior member of ACM, and a member of Sigma Xi.


Microfluidics-based biochips are revolutionizing laboratory procedures involving molecular biology. Advances in microfluidics technology offer exciting possibilities for high-throughput DNA sequencing analysis, protein crystallization, drug discovery, immunoassays, and environmental toxicity monitoring. Another emerging application area for microfluidics-based biochips is clinical diagnostics, especially the immediate point-of-care diagnosis of diseases.

Defect tolerance is a key requirement for biochips that are used for healthcare and environmental monitoring. There is a need to deliver the same level of computer-aided design (CAD) support to the biochip designer that the semiconductor industry now takes for granted. These CAD tools will allow designers to harness the new technology that is rapidly emerging for integrated biofluidics.

This talk will present early work on design and test techniques for microfluidic biochips. The speaker will describe synthesis tools that can map behavioral descriptions to a droplet-based microfluidic biochip and generate an optimized schedule of bioassay operations, the binding of assay operations to functional units, and the layout and droplet flow-paths for the biochip. Cost-effective testing techniques will be presented to detect faults after manufacture and during field operation. It will be shown how on-line and off-line reconfiguration techniques can be used to easily bypass faults once they are detected. Thus the biochip user can concentrate on the development of the nano- and micro-scale bioassays, leaving implementation details to design automation tools.


 Professor DANIEL D. GAJSKI University of California at Irvine www.cecs.uci.edu/~gajski

"New Strategies for System-Level Design"


Dan Gajski, a leader in the areas of embedded systems, design methodologies and languages, headed the research teams that created new design concepts, methodologies, tools and languages. He was instrumental in developing formalisms such as Y-chart, and numerous algorithms for high-level synthesis, the definition of the control-data-flow-graph (CDFG) and finite-state-machine with data (FSMD), system level languages such as SpecCharts and SpecC, and design tools such as SpecSyn and Embedded-System Environment. Many of these concepts have been adapted by academia and industry in the last 25 years.

Gajski directs the UCI Center for Embedded Computer Systems, with a research mission to incorporate embedded systems into automotive, communications, and medical applications. He has authored over 300 papers and numerous textbooks, including Principles of Digital Design (Englewood Cliffs, NJ: Prentice Hall, 1997) that has been translated into several languages.

He holds Dipl. Ing. and M.S. degrees in electrical engineering from the University of Zagreb, Croatia, and a doctoral degree in computer and information sciences from the University of Pennsylvania, Philadelphia. After 10 years as Professor at University of Illinois he has joined UCI, where he presently holds The Henry Samueli Endowed Chair in Computer System Design.


With complexities of Systems-on-Chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a system design out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure.

In order to find the solution, we will look first at the system gap between SW and HW designs and derive requirements for the system design flow that includes software as well as hardware. In order to enable new tools for model generation, simulation, synthesis and verification, the design flow has to be well defined with unique abstraction levels, model semantics and model transformations that correspond to design decisions made by designers. We will introduce the concept of model algebra that supports such a design flow and can serve as an enabler for the new approach in globally-collaborative system design and, consequently, global system industry.

In order to demonstrate our approach we will use MP3 example and show increased simplicity and huge productivity gains for complex systems. We will explain the benefits and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of billion-transistor systems to the basic principles of design science only.


 Professor JANUSZ RAJSKI Mentor Graphics Corporation

"Logic Diagnosis and Yield Learning"


Janusz Rajski received the Ph.D. degree in electrical engineering from the Poznań University of Technology, Poland, in 1982. He is a chief scientist and the director of engineering for the Design-for-Test products group at Mentor Graphics. He has published more than 150 research papers in these areas and is co-inventor of 22 US and international patents. He is also the principal inventor of Embedded Deterministic Test (EDT™) technology used in the first commercial test compression product TestKompress®. He is co-author of Arithmetic Built-In Self-Test for Embedded Systems published by Prentice Hall in 1997. He was co-recipient of the 1993 Best Paper Award for the paper on logic synthesis published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, co-recipient of the 1995 and 1998 Best Paper Awards at the IEEE VLSI Test Symposium, co-recipient of the 1999 and 2003 Honorable Mention Awards at the IEEE International Test Conference, as well as co-recipient of the 2006 IEEE Circuits and Systems Society Donald O. Pederson Outstanding Paper Award recognizing the paper on embedded deterministic test published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. He has served on technical program committees of various conferences. He is Program Chair of the 2007 IEEE International Test Conference.


In the past, logic diagnosis was primarily used to support failure analysis labs. It was typically done on a small sample of defective chips, therefore long processing times, manual generation of diagnostic patterns, and usage of expensive equipment was acceptable. In addition to failure analysis, yield learning relied on test chips and in−line inspection. Recently, sub-wavelength lithography processes have started introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in the process. Test chips are no longer able to represent the various failure mechanisms originating from critical features. The number of such features is too large to properly represent it on silicon in a cost-effective manner. For new processes it is also impossible to predict all significant features up front. With the decreasing sizes of defects and increasing percentage of invisible ones, in−line inspection data is not always available.

To compensate for fading effectiveness of classical yield learning methods, new solutions are emerging that use logic diagnosis to turn production material into vehicles for yield learning. High-volume diagnosis is combined with the newly emerging field of design for manufacturing to make the analysis layout aware. This new approach offers a lot of advantages but it also presents many challenges from efficient collection of massive amounts of fail log data in production environment, fast and accurate diagnosis in test compression, links to process and lithography simulation, statistical post-processing of the results, and calculation of feature failure rates. Analysis of test data from manufacturing test is a true goldmine of information to calibrate, today largely qualitative, DFM rules and compute yield sensitivity functions. By closing the loop between DFM techniques and the actual defect behavior there is the potential to not only improve yield but also provide validation and calibration of DFM rules.

 2007 IEEE DDECS Workshop service.  Last changes: July 23rd, 2007.   Webmaster
On-line   [ ]