DDECS-2007: April 11-13, Cracow, Poland The 10th IEEE Workshop on
Design and Diagnostics of Electronic
Circuits and Systems


April 11-13, 2007
Kraków, Poland

   Programme of 2007 IEEE DDECS Workshop.

 

2007 IEEE DDECS - TIMETABLE
TUESDAY, ( April 10th )
17:00 - 22:00  Opening hours of Conference Registration Desk in Collegium Novum   (ul. Gołębia 24)
19:00 - 20:00  Welcome Reception at City Hall   ( Plac Wszystkich Świętych 3/4 )
20:00 - 20:45  Kraków by night - guided tour
WEDNESDAY, ( April 11th )
7:30 - 19:00  Opening hours of Conference Registration Desk in Collegium Novum   (ul. Gołębia 24)
8:30 - 08:50  DDECS & CCE chairs - Openning DDECS07 and CCE07  DDECS and CCE Welcome
8:50 - 09:40  Daniel Gajski, University of California at Irvine  Keynote talk in Collegium Novum
9:40 - 10:10  Coffee break
10:10 - 10:20  DDECS Program Chair  Technical Programme Introduction
10:20 - 11:20  Session I  DfT & Defect Analysis
11:20 - 12:40  Session II  SOC Design & Test
12:40 - 14:10  Lunch - Main Market Square - Hawelka Restaurant   ( Rynek Główny  34 )
14:10 - 15:30  Session III  Fault Analysis & Circuit Reliability
15:30 - 16:30  Session IV  FPGA-Based Design
16:30 - 17:30  Coffee break + Poster Session I
17:30 - 18:50  Session V  Memory Testing
18:50 - 19:10  Philippe Reynaert, EC, DG INFSO Embedded Systems  European Commission note
20:00 - 22:00  Welcome Dinner - Main Market Square - Wierzynek restaurant   ( Rynek Główny  15 )
THURSDAY, ( April 12th )
8:00 - 13:30  Opening hours of Conference Registration Desk in Collegium Novum   (ul. Gołębia 24)
8:30 - 09:20  Janusz Rajski, Mentor Graphics Corp.  Keynote talk in Collegium Novum
9:20 - 10:20  Session VI  Logic Design
10:20 - 11:20  Coffee break + Poster Session II + Sponsor session
11:20 - 11:40  Yervant Zorian, Virage Logic  IEEE Computer Society & TTTC note
11:40 - 12:20  Session VII  Fault Tolerance I
12:20 - 13:20  Session VIII  Analog & RF Design
13:20 - 14:50  Lunch - Main Market Square - Hawelka Restaurant   ( Rynek Główny  34 )
14:50 - 20:00  Social event
20:00 - 23:50  Banquet
FRIDAY, ( April 13th )
8:00 - 16:30  Opening hours of Conference Registration Desk in Collegium Novum   (ul. Gołębia 24)
8:30 - 09:50  Session IX  Fault Tolerance II
9:50 - 10:50  Coffee break + Poster Session III
10:50 - 11:40  Krishnendu Chakrabarty, Duke University  Keynote talk in Collegium Novum
11:40 - 12:40  Session X  Test Quality & Test Generation
12:40 - 14:10  Lunch - Main Market Square - Hawelka Restaurant   ( Rynek Główny  34 )
14:10 - 15:10  Session XI  Model Checking & Debugging
15:10 - 16:30  Session XII  Analog & MEMS testing
16:30 - 16:30  Workshop closing

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 Programme of 2007 IEEE DDECS Workshop 
  Keynote Presentations
 
New Strategies for System-Level Design
Daniel D. GAJSKI
 
Design and Test of Microfluidic Biochips
Krishnendu CHAKRABARTY
 
Logic Diagnosis and Yield Learning
Janusz RAJSKI
 
Session I [ WEDNESDAY, April 11th, 10:20 - 11:20 ]
  DfT & Defect Analysis
 
A Testable Random Bit Generator Based on a High Resolution Phase Noise Detection
Marco BUCCI (Infineon Technologies AG),  Raimondo LUZZI (Infineon Technologies AG)
 
Test Pattern Compression Based on Pattern Overlapping
Jiři JENÍČEK  (Technical University of Liberec),  Ondřej NOVÁK (Technical University of Liberec)
 
Layout to Logic Defect Analysis for Hierarchical Test Generation
Maksim JENIHHIN (Tallinn University of Technology),  Jaan RAIK (Tallinn University of Technology),  Raimund UBAR (Tallinn University of Technology),  Witold A. PLESKACZ (Warsaw University of Technology),  Michał RAKOWSKI (Warsaw University of Technology)
 
Session II [ WEDNESDAY, April 11th, 11:20 - 12:40 ]
  SOC Design & Test
 
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips
Bartosz WOJCIECHOWSKI (Evatronix SA),  Tomasz KOWALCZYK (Evatronix SA),  Wojciech SAKOWSKI (Silesian University of Technology)
 
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs
Radosław CZARNECKI (Cracow University of Technology),  Stanisław DENIZIAK (Cracow University of Technology)
 
Extended Fault Detection Techniques for Systems-on-Chip
Paolo BERNARDI (Politecnico di Torino),  Leticia BOLZANI (Politecnico di Torino),  Matteo SONZA REORDA (Politecnico Di Torino)
 
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
Anders LARSSON (IDA),  Erik LARSSON (Linköpings Universitet),  Petru ELES (Linköpings Universitet),  Zebo PENG (Linköpingss Universitet)
 
Session III [ WEDNESDAY, April 11th, 14:10 - 15:30 ]
  Fault Analysis & Circuit Reliability
 
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance
Saibal MUKHOPADHYAY (Purdue University),  Qikai CHEN (Purdue University),  Kaushik ROY (Purdue University)
 
Architecture for Highly Reliable Embedded Flash Memories
Benoît GODARD (Atmel Rousset‚ LIRMM),  Jean Michel DAGA (Atmel Rousset),  Lionel TORRES (LIRMM),  Gilles SASSATELLI (LIRMM)
 
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology
Zhicheng LIANG (The University of Tokyo),  Makoto IKEDA (The University of Tokyo),  Kunihiro ASADA (The University of Tokyo)
 
Accurately Determining Bridging Defects from Layout
Maria GKATZIANI (Synopsys‚ Inc.),  Rohit KAPUR (Synopsys‚ Inc.),  Qing SU (Synopsys‚ Inc.),  Ben MATHEW (Synopsys‚ Inc.),  Roberto MATTIUZZO (STMicroelectronics Srl.),  Laura TARANTINI (STMicroelectronics Srl.),  Cy HAY (Synopsys‚ Inc.),  Salvatore TALLUTO (Synopsys‚ Inc.),  Thomas W. WILLIAMS (University of Calgary)
 
Session IV [ WEDNESDAY, April 11th, 15:30 - 16:30 ]
  FPGA-Based Design
 
FPGA Implementation of Strongly Parallel Histogram Equalization
Ernest JAMRO (AGH University of Sience and Technollogy),  Maciej WIELGOSZ (AGH University of Science and Technology),  Kazimierz WIATR (AGH University of Science and Technology)
 
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA’s
Grzegorz BOROWIK (Warsaw University of Technology),  Bogdan FALKOWSKI (Nanyang Technological University),  Tadeusz ŁUBA (Warsaw University of Technology) 
 
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder
Ari KULMALA (Tampere University of Technology),  Erno SALMINEN (Tampere University of Technology),  Timo D. HÄMÄLÄINEN (Tampere University of Technology)
 
Coffee break + Poster Session I [ WEDNESDAY, April 11th, 16:30 - 17:30 ]
 
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling
Dongsoo KIM (Yonsei University),  Gunhee HAN (Yonsei University)
 
A PMT Interface for the Optical Module Front-end of a Neutrino Underwater Telescope
Valeria SIPALA (Istituto Nazionale di Fisica Nucleare),  Domenico LO PRESTI (Istituto Nazionale di Fisica Nucleare‚ Università degli studi di Catania),  Nunzio RANDAZZO (Istituto Nazionale di Fisica Nucleare),  Luigi CAPONETTO (Istituto Nazionale di Fisica Nucleare)
 
A Proposal for ASM++ Diagrams
Santiago DE PABLO (University of Valladolid),  Santiago CÁCERES (University of Valladolid),  Jesús A. CEBRIÁN (University of Valladolid),  Manuel BERROCAL (eZono GmbH)
 
Lightweight Multi-threaded Network Processor Core in FPGA
Piotr BUCIAK (Warsaw University of Technology),  Jakub BOTWICZ (Warsaw University of Technology)
 
Parts Obsolescence Challenges for the Electronics Industry
Jim TORRESEN (University of Oslo),  Thor Arne LOVLAND (University of Oslo)
 
Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application
Khalil ARSHAK (University of Limerick),  Francis ADEPOJU (University of Limerick),  Essa JAFER (University of Limerick)
 
Two-level Logic Synthesis for Low Power Based on New Model of Power Dissipation
Ireneusz BRZOZOWSKI (AGH University of Science and Technology),  Andrzej KOS (AGH University of Science and Technology)
 
A March-based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories
Gurgen HARUTUNYAN (Virage Logic),  Valery A. VARDANIAN (Virage Logic),  Yervant ZORIAN (Virage Logic)
 
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing
Tomasz GARBOLINO (Silesian University of Technology),  Krzysztof GUCWA (Silesian University of Technology),  Michał KOPEĆ (Silesian University of Technology),  Andrzej HŁAWICZKA (Silesian University of Technology in Gliwice)
 
Instance Generation for SAT-based ATPG
Daniel TILLE (University of Bremen),  Görschwin FEY (University of Bremen),  Rolf DRECHSLER (University of Bremen)
 
Power Testing of an FPGA-based System Using Modelsim Code Coverage Capability
Khalil ARSHAK (University of Limerick),  Essa JAFER (University of Limerick),  Christian IBALA (XILINX)
 
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects
Ajoy K. PALIT (University of Bremen),  Kishore K. DUGANAPALLI (University of Bremen),  Walter ANHEIER (University of Bremen)
 
Session V [ WEDNESDAY, April 11th, 17:30 - 18:50 ]
  Memory Testing
 
Built in Defect Prognosis for Embedded Memories
Prashant DUBEY (STMicroelectronics),  Akhil GARG (STMicroelectronics),  Sravan Kumar BHASKARANI (STMicroelectronics)
 
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories
Luigi DILILLO (University of Southampton),  Bashir M. AL−HASHIMI (University of Southampton)
 
Manifestation of Precharge Faults in High Speed DRAM Devices
Zaid AL−ARS (Delft University of Technology),  Said HAMDIOUI (Delft University of Technology),  Georgi GAYDADJIEV (Delft University of Technology)
 
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
Philipp ÖHLER (University of Paderborn),  Sybille HELLEBRAND (University of Paderborn),  Hans−Joachim WUNDERLICH (University of Stuttgart)
 
Session VI [ THURSDAY, April 12th, 9:20 - 10:20 ]
  Logic Design
 
An Improved MDCT IP Core Generator with Architectural Model Simulation
Peter MALÍK (Slovak Academy of Sciences),  Marcel BALÁŽ (Slovak Academy of Sciences),  Tomáš PIKULA (Slovak Academy of Sciences),  Martin ŠIMLAŠTÍK (Slovak Academy of Sciences)
 
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
Chiou−Kou TUNG (National Chinyi Institute of Technology),  Yu−Cherng HUNG (National Chinyi Institute of Technology),  Shao−Hui SHIEH (National Chinyi Institute of Technology),  Guo−Shing HUANG (National Chinyi Institute of Technology)
 
Automatic Generation of Circuits for Approximate String Matching
Tomáš MARTÍNEK (Brno University of Technology),  Otto FUČÍK (Brno University of Technology),  Patrik BECK (CESNET z.s.p.o.),  Matej LEXA (Masaryk University)
 
Coffee break + Poster Session II + Sponsor session [ THURSDAY, April 12th, 10:20 - 11:20 ]
 
About the Efficiency of Real Time Sequences FFT Computing
Costin CEPIŞCĂ (Politehnica University of Bucharest),  Sorin Dan GRIGORESCU (Politehnica University of Bucharest),  Mircea COVRIG (Politehnica University of Bucharest),  Horia ANDREI (Valahia University of Targoviste)
 
Clockless Implementation of LEON2 for Low-Power Applications
Martin ŠIMLAŠTÍK (Slovak University of Technology),  Viera STOPJAKOVÁ (Slovak University of Technology),  Libor MAJER (Slovak University of Technology),  Peter MALÍK (Slovak Academy of Sciences)
 
Decomposition of Logic Functions in Reed-Muller Spectral Domain
Edward HRYNKIEWICZ (Silesian University of Technology),  Stefan KOŁODZIŃSKI (Pratt & Whitney)
 
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor
Alexandru AMĂRICĂI (Politehnica University of Timisoara),  Mircea VLĂDUŢIU (Politehnica University of Timisoara),  Lucian PRODAN (Politehnica University of Timisoara),  Mihai UDRESCU (Politehnica University of Timisoara),  Oana BONCALO (Politehnica University of Timisoara)
 
Establishing a New Course in Reconfigurable Logic System Design
Jim TORRESEN (University of Oslo),  Jorgen NORENDAL (University of Oslo),  Kyrre GLETTE (University of Oslo)
 
Power Dissipation in Basic Global Clock Distribution Networks
Artur Ł. SOBCZYK (Warsaw University of Technology),  Arkadiusz W. ŁUCZYK (Warsaw University of Technology),  Witold A. PLESKACZ (Warsaw University of Technology)
 
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters
Roman BAZYLEVYCH (Lviv Polytechynic National University − University of Information Technology and Management‚ Rzeszow),  Ihor PODOLSKYY (Lviv Polytechynic National University),  Lubov BAZYLEVYCH (Institute of Applied Physics and Mathematics of the National Academy of Science of Ukraine)
 
A Mixed Approach for Unified Logic Diagnosis
Alexandre ROUSSET (LIRMM),  Alberto BOSIO (LIRMM),  Patrick GIRARD (LIRMM),  Christian LANDRAULT (LIRMM),  Serge PRAVOSSOUDOVITCH (LIRMM),  Arnaud VIRAZEL (LIRMM)
 
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
Lukas SEKANINA (Brno University of Technology)
 
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services
Mohammad Hossein NEISHABURI (University of Tehran),  Mohammad Reza KAKOEE (University of Tehran),  M. DANESHTALAB (University of Tehran),  Saeed SAFARI (University of Tehran),  Zainalabedin NAVABI (University of Tehran)
 
Multiple Errors Detection Technique for RAM
Sergei B. MUSIN (Belarussian State University of Informatics and Radioelectronics),  Alexander A. IVANIUK (Belarussian State University of Informatics and Radioelectronics),  Vyacheslav N. YARMOLIK (Belarussian State University of Informatics and Radioelectronics)
 
Test Pattern Generator for Delay Faults
Tomasz RUDNICKI (Silesian University of Technology),  Andrzej HŁAWICZKA (Silesian University of Technology)
 
Session VII [ THURSDAY, April 12th, 11:40 - 12:20 ]
  Fault Tolerance I
 
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
Oscar RUANO (Universidad Antonio de Nebrija),  Pilar REYES (Universidad Antonio de Nebrija),  Juan A. MAESTRO (Universidad Antonio de Nebrija),  Luca STERPONE (Politecnico di Torino),  Pedro REVIRIEGO (Universidad Carlos III de Madrid)
 
A Novel Parity Bit Scheme for SBox in AES Circuits
Giorgio DI NATALE (LIRMM),  Marie−Lise FLOTTES (LIRMM),  Bruno ROUZEYRE (LIRMM)
 
Session VIII [ THURSDAY, April 12th, 12:20 - 13:20 ]
  Analog & RF Design
 
Designing Time-to-Digital Converter for Asynchronous ADCs
Dariusz KOŚCIELNIK (AGH University of Science and Technology),  Marek MIŚKOWICZ (AGH University of Science and Technology)
 
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization
Lukáš RUČKAY (ASICentrum‚ CTU Prague),  Jiří NEDVĚD (ASICentrum)
 
RF Transformer Model Parameters Measurement
Vytautas DUMBRAVA (Kaunas University of Technology),  Linas SVILAINIS (Kaunas University of Technology)
 
Session IX [ FRIDAY, April 13th, 8:30 - 09:50 ]
  Fault Tolerance II
 
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
Jorge SEMIÃO (IST/INESC−ID‚ University of Algarve),  J. FREIJEDO (IST/INESC−ID‚ University of Vigo),  Juan J. RODRÍGUEZ−ANDINA (University of Vigo),  Fabian VARGAS (Catholic University − PUCRS),  Marcelino Bicho SANTOS (IST/INESC−ID Lisboa),  Isabel Maria CACHO TEIXEIRA (IST/INESC−ID Lisboa),  Joao Paulo TEIXEIRA (IST/INESC−ID Lisboa)
 
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs
Manuel G. GERICOTA (ISEP\LABORIS),  Luís F. LEMOS (ISEP\LABORIS),  Gustavo R. ALVES (ISEP\LABORIS),  José M. FERREIRA (University of Porto)
 
Flip-Flops and Scan-Path Elements for Nanoelectronics
Rene KOTHE (Brandenburg University of Technology Cottbus),  Heinrich T. VIERHAUS (Brandenburg University of Technology Cottbus)
 
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair Facility via Variable Accuracy Arithmetic
Paweł PAWŁOWSKI (Poznań University of Technology),  ADAM DĄBROWSKI  (Poznań University of Technology),  Mario SCHÖLZEL (Brandenburg University of Technology)
 
Coffee break + Poster Session III [ FRIDAY, April 13th, 9:50 - 10:50 ]
 
Dedicated Architecture for Double Precision Matrix Multiplication in Supercomputing Environment
Paweł RUSSEK (AGH University of Science and Technology),  Kazimierz WIATR (AGH University of Science and Technology)
 
Design Issues of a Low Frequency Low-Pass Filter for Medical Applications Using CMOS Technology
András TIMÁR (Budapest University of Technology and Economics),  Márta RENCZ (Budapest University of Technology and Economics)
 
Feasibility of Image Compression in FPGA-based Neural Networks
Vladimir HAVEL (VŠB − Technical University of Ostrava),  Karel VLČEK (VŠB − Technical University of Ostrava)
 
IP Integration Overhead Analysis in System-on-Chip Video Encoder
Antti RASMUS (Tampere University of Technology),  Ari KULMALA (Tampere University of Technology),  Erno SALMINEN (Tampere University of Technology),  Timo D. HÄMÄLÄINEN (Tampere University of Technology)
 
Quadrature-Phase Topology of a High Frequency Ring Oscillator
Ábel VÁMOS (Budapest University of Technology and Economics)
 
Reticle Exposure Plans for Multi-Project Wafers
Rung−Bin LIN (Yuan Ze University),  Da−Wei HSU (Yuan Ze University),  Ming−Hsine KUO (Yuan Ze University),  Meng−Chiou WU (Yuan Ze University)
 
Low Cost, Low Power, Intelligent Brake Temperature Sensor System for Automotive Applications
Gyula BAKONYI−KISS (Budapest University of Technology and Economics),  Zoltan SZUCS (Budapest University of Technology and Economics)
 
Determining MOSFET Parameters in Moderate Inversion
Matthias BUCHER (Technical University of Crete),  Antonios BAZIGOS (National Technical University of Athens),  Władysław GRABIŃSKI (MOS−AK)
 
Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization
Tomasz GOLONEK (Silesian University of Technology),  Damian GRZECHCA (Silesian University of Technology),  Jerzy RUTKOWSKI (Silesian University of Technology)
 
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
Pavel KUBALÍK (Czech Technical University in Prague),  Jiří KVASNIČKA (Czech Technical University in Prague),  Hana KUBÁTOVÁ (Czech Technical University in Prague)
 
Intrusion Detection System Intended for Multigigabit Networks
Jan KOŘENEK (Brno University of Technology),  Petr KOBIERSKÝ (CESNET − z. s. p. o.)
 
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-micron Integrated Circuit
Włodzimierz JOŃCA (Warsaw University of Technology)
 
Session X [ FRIDAY, April 13th, 11:40 - 12:40 ]
  Test Quality & Test Generation
 
Transition Faults Testing Based on Functional Delay Tests
Eduardas BAREIŠA (Kaunas University of Technology),  Vacius JUSAS (Kaunas University of Technology),  Kęstutis MOTIEJUNAS (Kaunas University of Technology),  Rimantas ŠEINAUSKAS (Kaunas University of Technology)
 
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits
Aristides EFTHYMIOU (University of Edinburgh)
 
Prototyping Generators for On-line Test Vector Generation Based on PSL Properties
Yann ODDOS (Tima Laboratory),  Katell MORIN−ALLORY (Tima Laboratory),  Dominique BORRIONE (Tima Laboratory)
 
Session XI [ FRIDAY, April 13th, 14:10 - 15:10 ]
  Model Checking & Debugging
 
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata
Marc HERBSTRITT (Albert−Ludwigs−University Freiburg im Breisgau),  Bernd BECKER (Albert−Ludwigs−University Freiburg im Breisgau),  Erika ÁBRAHÁM (Albert−Ludwigs−University Freiburg im Breisgau),  Christian HERDE (Carl−von−Ossietzky University‚ Oldenburg)           
 
SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse
Fabricio V. ANDRADE (Universidade Federal de Minas Gerais‚ Centro Federal de Educação Tecnológica de Minas Gerais),  Márcia C. M. OLIVEIRA (Universidade Federal de Minas Gerais),  Antônio O. FERNANDES (Universidade Federal de Minas Gerais),  Claudionor José N. COELHO Jr. (Universidade Federal de Minas Gerais)
 
Debug Patterns for Efficient High-level SystemC Debugging
Frank ROGIN (Fraunhofer IIS / EAS Dresden),  Erhard FEHLAUER (Fraunhofer IIS / EAS Dresden),  Christian HAUFE (AMD Saxony LLC & Co. KG),  Sebastian OHNEWALD (AMD Saxony LLC & Co. KG)
 
Session XII [ FRIDAY, April 13th, 15:10 - 16:30 ]
  Analog & MEMS testing
 
Memory Based Analogue Signal Generation Implementation Issues for BIST
Thomas O. SHEA (University of Limerick),  Ian GROUT (University of Limerick),  Jeffrey RYAN (University of Limerick)
 
Developing Virtual ADC Testing Environment in MAPLE
Petr STRUHOVSKÝ (Czech Technical University in Prague),  Ondřej ŠUBRT (Czech Technical University in Prague; ASICentrum),  Jiří HOSPODKA (Czech Technical University in Prague),  Pravoslav MARTINEK (Czech Technical University in Prague)
 
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing
Zbigniew PIĄTEK (Warsaw University of Technology),  Jerzy F. KOŁODZIEJSKI (Institute of Electron Technology),  Witold A. PLESKACZ (Warsaw University of Technology)
 
MEMS Testing by Vibrating Capacitor
Jãnos MIZSEI (Budapest University of Technology and Economics),  M. REGGENTE (Budapest University of Technology and Economics)
 
 2007 IEEE DDECS Workshop service.  Last changes: July 23rd, 2007.   Webmaster
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